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DMA controller (DMA)
Figure 24. DMA2 request mapping
Peripheral request signals
TIM5_CH4
Fixed hardware priority
HIGH PRIORITY
RM0008
TIM5_TRIG
TIM8_CH3
TIM8_UP
HW request 1
SW trigger (MEM2MEM bit)
Channel 1
SPI/I2S3_RX
Channel 1 EN bit
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM5_CH3
TIM5_UP
HW request 2
SW trigger (MEM2MEM bit)
Channel 2
SPI/I2S3_TX
Channel 2 EN bit
TIM8_CH1
UART4_RX
TIM6_UP/DAC_Channel1
HW request 3
SW trigger (MEM2MEM bit)
Channel 3 EN bit
Channel 3
internal
DMA2
TIM5_CH2
SDIO
TIM7_UP/DAC_Channel2
HW request 4
SW trigger (MEM2MEM bit)
Channel 4
request
Channel 4 EN bit
ADC3
TIM8_CH2
HW request 5
Channel 5
TIM5_CH1
UART4_TX
SW trigger (MEM2MEM bit)
LOW PRIORITY
Channel 5 EN bit
Table 58 lists the DMA2 requests for each channel.
Table 58.
Summary of DMA2 requests for each channel
Peripherals
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
ADC3 (1)
ADC3
SPI/I2S3
SPI/I2S3_RX
SPI/I2S3_TX
UART4
UART4_RX
UART4_TX
SDIO
(1)
SDIO
TIM5
TIM5_CH4
TIM5_TRIG
TIM5_CH3
TIM5_UP
TIM5_CH2
TIM5_CH1
TIM6/
DAC_Channel1
TIM7/
DAC_Channel2
TIM6_UP/
DAC_Channel1
TIM7_UP/
DAC_Channel2
TIM8 (1)
TIM8_CH3
TIM8_UP
TIM8_CH4
TIM8_TRIG
TIM8_COM
TIM8_CH1
TIM8_CH2
1. ADC3, SDIO and TIM8 DMA requests are available only in high-density devices.
190/995
Doc ID 13902 Rev 9
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